Monday, 28 November 2011

Bonnell micro-architecture

Intel Atom processors are based on Bonnell micro-architecture which can execute up to two instructions per cycle. Like many other x86 microprocessors, it translates x86-instructions (CISC instructions) into simpler internal operations (sometimes called as micro-ops, i.e., effectively RISC style instructions) before execution.

Processor logic is implemented on silicon chips according to the kind of operations it has to perform(instructions). CISC instructions or complex instructions needs more chip area. More chip area increases power consumption. RISC are simpler type of instructions which require less chip area for implementation. It also reduces power requirement.

In Atom processors the majority of instructions produce one micro-op when translated. Around 4% of instructions used in typical programs produce multiple micro-ops. The number of instructions that produce more than one micro-op is fewer than in P6 (Pentium 3) and NetBurst (Pentium 4 and related) micro-architectures. The Bonnell micro-architecture therefore represents a partial revival of the principles used in earlier Intel designs such as P5 and the i486, with the sole purpose of enhancing the performance per watt ratio. However, Hyper-Threading is implemented in an easy (i.e., low power) way to employ both pipelines efficiently by avoiding the typical single thread dependencies.

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